Computer bus architectures have evolved over time to provide increasing amounts of bandwidth for communications between computer components. For example, in the 1980's, the Industry Standard Architecture (ISA) bus provided a 16-bit interface operated at 8 MHz. Eventually, the ISA bus was replaced or enhanced by other bus architectures such as the Microchannel (MCA) bus, the Extended ISA (EISA) bus, and the Video Electronics Standards Association (VESA) Local Bus (VL-bus). To further improve bandwidth, the Peripheral Component Interconnect (PCI) architecture was developed to provide a 32-bit interface operated at 33 MHz. PCI Express (PCIe) is now being widely implemented between communication links in servers or personal computers. The PCI Special Interest Group (PCI-SIG) has recently released the updated PCI Express 2.0 Specification, which supports data transfer rates of 5 gigatransfers/second, where every eight bits are encoded into a 10-bit symbol (8 b/10 b encoding).
As data transfer rates increase to 5 gigatransfers/second and beyond, various design requirements need to be met to ensure successful communication. One of these design requirements is the synchronization of clocks for paired transmitter (TX) and receiver (RX) communication links. Rather than require perfect synchronization, bus architectures such as PCI Express 2.0 specify various design budgets including a clock jitter budget. Other examples of design budgets include thresholds for printed circuit board (PCB) trace characteristics and the distance between communication links.
It is known that some clock-jitter is due to imperfections, thermal noise and/or differences in the design of Phase-Locked Loops (PLLs), which are used by communication links to increase a reference clock signal (e.g., 100 MHz) to a desired communication link clock signal (e.g., 5 GHz). Efforts to improve the design of PLLs or to otherwise reduce clock jitter are being made.